A conventional power rail coupling for an output buffer circuit 10 is illustrated in FIGS. 1-3. The output buffer circuit 10 delivers output signals of high and low potential levels H,L at an output V.sub.OUT in response to data signals at an input V.sub.IN. The output buffer circuit includes an input stage 12 coupled between a relatively quiet power supply rail V.sub.CCQ and a relatively quiet power ground rail GNDQ. An output stage 14 is coupled between a relatively noisy power supply rail V.sub.CCN and a relatively noisy power ground rail GNDN. By way of example, in the BICMOS output buffer circuits described in the related Patent Applications, the input stage 12 is composed of CMOS transistors providing a relatively high impedance input, while the output stage 14 is composed of bipolar transistors providing a relatively low impedance output.
The relatively quiet and noisy supply rails V.sub.CCQ, V.sub.CCN are coupled to respective spaced apart bond pads 20,22 on the integrated circuit chip. The supply rail bond pads, 20,22 are in turn coupled by separate bonding wires to separate leadframe fingers 24,25 of the leadframe. Similarly the relatively quiet and noisy power ground rails GNDQ,GNDN are coupled to spaced apart bond pads 30,32 on the IC chip. The ground rail bond pads 30,32 are coupled by separate bonding wires to separate leadframe fingers 34,35 of the leadframe.
As shown in FIGS. 2 & 3, the leadframe may be a split lead leadframe with split power leads providing partial isolation of the relatively quiet and noisy power rails. In FIG. 2 the split leads 24,25 for the respective quiet and noisy supply rails V.sub.CCQ, V.sub.CCN, merge at a common segment 26 and common V.sub.CC pin 28 for coupling to the external power supply V.sub.CC. In FIG. 3 the split leads 34,35 for the respective quiet and noisy ground rails GNDQ,GNDN merge at a common segment 36 and common GND pin 38 for coupling to external ground GND.
Such leadframe split leads or split leadframe fingers for relative isolation of internal and output supply rails and ground rails are further described in the Ray A. Mentzer et al. U.S. Pat. No. 5,065,224 issued Nov. 12, 1991 for LOW NOISE INTEGRATED CIRCUIT AND LEADFRAME, filed in the USPTO on Sep. 8, 1988, an FWC Continuation of U.S. patent application Ser. No. 880,407 for REDUCTION IN POWER RAIL PERTURBATION filed Jun. 30, 1986, now abandoned. Other types of split lead leadframes are described in the Natsui Japan Patent Document 57-164548 dated Oct. 9, 1982, and the Watanabe European Patent Application 86901518.0filed in the EPO Feb. 28, 1986, corresponding to International Application No. PCT/JP86/00106 published Sep. 12, 1986 as International Publication No. WO86/05322.
An equivalent circuit is shown in FIG. 2A for the split lead leadframe fingers 24,25 and common stem 26 for partial isolation of the relatively quiet and noisy supply rails V.sub.CCQ, V.sub.CCN. The split lead configuration partially isolates internal stages of the IC chip and input stage 12 from the noise problems caused by sourcing and sinking large currents at the output. These noise problems are analyzed in further detail in the Alan C. Rogers U.S. Pat. No. 5,049,763 issued Sep. 17, 1991 for ANTI-NOISE CIRCUITS.
Briefly, upon transition from low to high potential at the output, an output pullup transistor of the output stage 14 becomes conducting with a surge or acceleration of charge from the external power supply V.sub.CC to the output V.sub.OUT through the common lead inductance L.sub.CV of the common stem 26 of the split lead leadframe fingers 24,25, and the separate lead inductance L.sub.NV of the split lead 25. The split lead 25 becomes the relatively noisy power supply V.sub.CCN. The parasitic inductive impedance and resulting voltage across the inductances L.sub.CV, L.sub.NV causes transient drop in the noisy output supply rail V.sub.CCN of for example as great as 2.5 volts below the external power supply V.sub.CC voltage of 5 volts. This drop in the noisy power supply V.sub.CCN voltage level is referred to as V.sub.CC droop, V.sub.CC collapse and consequent V.sub.OHV at the output. V.sub.CC droop causes a corresponding delay in the LH voltage rise at the output V.sub.OUT which appears as a "step" in the output voltage wave form illustrated in the graph of FIG. 7 and referred to herein as "output step" in the voltage level transition. Only a substantially smaller V.sub.CC droop appears on the relatively quiet supply rail V.sub.CCQ split lead 24 because of the relative isolation of the V.sub.CCQ split lead 24 inductance L.sub.QV from the relatively noisy supply rail V.sub.CCN and split lead 25 inductance L.sub.NV.
Deceleration of the initial surge of charge through the output pullup transistor of output stage 14 results in a following supply rail voltage overshoot in the relatively noisy supply rail V.sub.CCN split lead 25 of opposite polarity from V.sub.CC droop. Subsequent ringing may persist until the inertial energy of the supply lead inductances is dissipated in the output transistors and related circuit components. Similar noise problems appear on the power ground side of the output buffer circuit in the relatively noisy ground rail GNDN and corresponding split lead 35, referred to as ground bounce and undershoot further analyzed in U.S. Pat. No. 5,049,763 referenced above.
In addition to split lead leadframe configurations, integrated circuit chips and chip packages are also available with entirely separate quiet and noisy ground rails and leads and entirely separate quiet and noisy supply rails and leads for better separation. In such leadframes, internal and output ground rails GNDQ,GNDN are routed to external ground through entirely separate leadframe fingers and separate pins. Similarly internal and output supply rails are coupled to the external power supply through entirely separate leadframe fingers and pins. This increases the isolation or separation of relatively quiet and noisy power rails in comparison with the split lead leadframe configurations.
The prior art isolation of relatively quiet internal power rails from relatively noisy output power rails is advantageous particularly in circuit applications where multiple output buffers are coupled to a common bus. The relative isolation of the shared quiet and noisy output leads helps to preserve and maintain the input dynamic threshold voltage level of quiet or non-switching buffer circuits coupled to the common bus while other output buffer circuits are switching. Without sufficient isolation of the relatively quiet and noisy power rails, the resulting variation in the input dynamic threshold voltage level at which switching may occur at the quiet output buffer circuits may cause false signals at a quiet output V.sub.QOUT.
By way of example, for the BICMOS output buffer circuits described in the related patent applications, the typical input dynamic threshold voltage level V.sub.T at which switching of the buffer circuit occurs is for example approximately 1.5 volts at the input V.sub.IN. When the output buffer circuit is holding a high potential level signal H at the output V.sub.QOUT, the input dynamic threshold voltage level V.sub.IHD may be in the range of between 1.5 to 2.0 volts. While the output buffer circuit is holding a low potential level signal L at the output (V.sub.QOUT), the input dynamic threshold voltage level may be in the range of 0.8 to 1.5 volts at the input.
Without isolation, noise in the power rails may otherwise force the input dynamic threshold voltage level outside of the respective ranges causing switching events and false data signals at the output. For a high potential level signal H held at the output V.sub.QOUT, a dip in voltage below, for example, 2 volts is a failure. Similarly for a low potential level signal L held at the output V.sub.QOUT, a rise in output voltage above 0.8 volts is a failure.
While isolation of the power rails prevents such input dynamic threshold failures, it also accentuates V.sub.CC droop or V.sub.CC crash in the output supply rail V.sub.CCN. The isolation of power rails also accentuates ground bounce in the relatively noisy ground rail GNDN. This is because parasitic inductance is increased by splitting and isolating the rails, thereby increasing parasitic noise. This in turn accentuates output step and consequent delay in LH or HL transitions at the output.